This invention relates to an information processing system having an improved interface unit connected between an information processing unit and an input/output unit.
It has been the practice to install a first-in first-out stack (FIFO) acting as a data buffer between an information processing unit such as a microcomputer and an input/output unit. Such FIFO stack is constructed to generate a "FULL" signal representing that the memory unit of the stack is full of information and an "EMPTY" signal representing that there is no information stored in the stack. Usually the FIFO stack comprises a plurality of cascade connected memory elements and is constructed such that an information initially stored in a memory element of the first stage is firstly derived out from the memory element of the last stage.
In the prior art information processing system it has been necessary to arrange a circuit including a register between a FIFO stack and an information processing unit for the purpose of detecting the state of the FIFO stack by the information processing unit. There has also been proposed a method wherein the state of the FIFO stack is indirectly detected by detecting the state of the terminal unit by the information processing unit. In this case, it is not necessary to use a circuit including a register as above described but it is necessary to constantly watch the state of the terminal unit. Accordingly, the circuit utilized to this end is complicated.